Ultra-low power digital subthreshold logic circuits pdf

Recently, digital subthreshold circuit design has become a very promising method for ultralow power applications. The institute of electronics, information and communication engineers produced and listed by. Mos current mode logic mcml in subthreshold operation is explored for the purpose of ultra low power clock generation. Physics of power dissipations and parameter variations. While several techniques for implementing cmos logic circuits with transistors in the subthreshold regime and with very low power dissipation have been already introduced 1, the design of mcml circuits operating in. The paper explores basics of subthreshold, sources of power dissipation, challenges in subthreshold design, optimization methodology and various types of techniques which are currently used to implement ultra low power based circuits using subthreshold logic. In this paper, we investigate different logic families in subthreshold region for ultralow power applications. However, in 6545 nm cmos, variability and shortchannel effects signi. Device and circuit design challenges in the digital. Subthreshold and nearthreshold techniques for ultralow power. As the integration, size, and complexity of the chips continue to increase, the difficulty in providing adequate cooling might either add.

A subthreshold circuit also consumes less power than other known lowpower circuits, such as energy recovery logic 4. However, the design of ultra lowpower mcmlbased circuits remains an important challenge. Subthreshold sourcecoupled logic circuits for ultra low power applications article pdf available in ieee journal of solidstate circuits 437 august 2008 with 708 reads how we measure reads. Offers comprehensive coverage of modeling, analysis and design methodology for low power and variationtolerant logic circuits, memory and systems, microarchitecture, dsp.

Introduction in the medium performance, medium power consumption design region, numerous optimization efforts have been made1,2,3. Subthreshold sourcecoupled logic 1, 2, 3 has been proposed as an alternative to cmos in ultralow power applications, due to the precise control it o ers over speed and power consumption. The effective gate capacitance of a transistor is dominated by intrinsic depletion and parasitic capacitances, which are strongly dependent on. Kosonocky, optimal supply and threshold scaling for subthreshold cmos circuits, symposium on vlsi, pp. Pushing ultralowpower digital circuits into the nanometer era david bol. Ultra low power electronics and adiabatic solutions. It is an accepted fact that circuits operating in the subthreshold regionrun at significantly lowfrequencies e. Digital subthreshold logic circuits can be used for applications in the ultralow power end of the design spectrum, where performance is of secondary importance. The digital logic and the avs control circuitry are designed in 65nm cmos for an image processing application. Pdf ultra low power clock generation using subthreshold.

The subthreshold logic can be easily implemented and derived from existing circuits by lowering the power supply voltage to be less than threshold voltage. Understanding subthreshold source coupled logic for ultra. We compare the results with cmos in normal strong inversion region and with other known low power logic, namely, energy recovery logic. This substantiates the approach taken in 10 where standard cell libraries are used to design circuits for subthreshold operations withminimalmodification. Numerous efforts in balancing the tradeoff between power, area and performance have been done in the medium performance, medium power region of the design spectrum. This article presents a novel approach for implementing ultralow power digital components and systems using sourcecoupled logic scl circuit topology, operating in weak inversion subthreshold regime. Leakage current reduction using subthreshold sourcecoupled logic armin tajalli, student member, ieee, and yusuf leblebici, senior member, ieee abstractthe performance of subthreshold sourcecoupled logic stscl circuits for ultralow power applications is explored. Ultralow power digital subthreshold logic circuits abstract.

One solution to achieve the ultralow power requirement is to operate the digital logic gates in subthreshold region. Pdf ultra low power subthreshold mos current mode logic. Ultralow subthreshold voltage research has become increasingly important with the recent shift in consumer electronics towards low power designs for mobile, wearable, and implantable technologies. Current mode logic cml, or sourcecoupled logic scl, is a differential digital logic family intended to transmit data at speeds between 312. To reduce these capacitances, higher value of is preferred. Digital subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of mos transistors to operate. Roy, ultralow power digital subthreshold logic circuits, islped, pp. Pdf digital subthreshold logic design motivation and challenges. A study on ultralow power and largescale design of. Ultralow power digital subthreshold logic circuits ieee.

Ultra lowpower subthreshold mos current mode logic. In this paper, analysis was done both cmos and pseudonmos logic families operating in sub. Abstractthis paper presents a novel approach for implementing ultralowpower digital components and systems using sourcecoupled logic scl circuit topology, operating in weak inversion subthreshold regime. To operate at very low bias currents, a simple and compact high. Sourcecoupled logic scl or mos currentmode logic mcml circuits for implementing mixedmode circuits. This leakage current is the main source of the static power consumption for digital circuits. Subthreshold circuit design for ultralowpower applications.

This thesis studies circuit design solutions that focus on. Implementation of ultralow power digital circuits using subthreshold adiabatic logic doi. A subthreshold digital circuit manages out how to fulfill the ultralow power. Recently, cml has been used in ultralow power applications.

Subsequently, an sclbased static randomaccess memory operating in weak inversion subthreshold region is implemented to demonstrate the performance of this topology for ultralowpower consumption and. In this paper, we studied different characteristics of digital logic circuits operating in subthreshold region to achieve ultralow power. Pmos transistors with shorted drainsubstrate contacts are used as gate controlled, very high resistivity load devices. Optimization and characterization of cmos for ultra low. The proposed technique is based on using subthreshold sourcecoupled or currentmode approach for both analog and digital circuits. Ultralow power digital subthreshold logic circuits acm digital. Robust subthreshold logic for ultralow power operation ieee xplore. Subthreshold digital circuits will be suitable for the. One of the primary requirements of a currentmode logic circuit is that the current bias transistor must remain in the saturation region in order to maintain a constant current. Ultralow power design of digital cmos logic circuits. In energy constraint subthreshold design, circuits are normally optimized to enhance the speed 18, 19. In the ultra low power end of design spectrum when performance is of secondary importance, digital subthreshold logic circuits are more applicable than the regular mos logic. This paper presents a novel approach for implementing ultralow power digital components and systems using sourcecoupled logic scl circuit topology, operating in weak inversion subthreshold regime. Lowpower variationtolerant design in nanometer silicon.

Subthreshold schmitt trigger using bodybias technique for. However, not much study has been done at the two ends of the design spectrum, namely ultralow power. Their combined citations are counted only for the first article. Digital sub threshold logic circuits can be functioned for applications in the ultralow power end of the outline range, where introduction is of minor significance. Ultra low energy cmos logic using belowthreshold dual. Subthreshold sourcecoupled logic circuits for ultra low. Pdf modified differential cascode voltage switch logic. Subthreshold logic transistors, that is the power supply voltage is below the threshold voltage. In this paper, we investigate different logic families in subthreshold region for ultralowpower applications. Agrawal department of ece, auburn university, auburn, al 36849, usa received. In recent years, subthreshold operation has gained a lot of attention due to ultra lowpower consumption in applications requiring low to medium performance.

Subthreshold sourcecoupled logic circuits for ultralowpower applications. Pdf ultralow power digital system design using subthreshold. More recently, the design of digital subthreshold logic was investigated with transistors operated in the subthreshold region. Design the ultralow power digital subthreshold logic. Pdf subthreshold sourcecoupled logic circuits for ultra low. Design and analysis of doublegate mosfets for ultralow. Understanding subthreshold source coupled logic for ultralow power application abstract this thesis work primarily focuses on the applicability of subthreshold source coupled logic stscl for building digital circuits and systems that run at very low voltage and promise to provide desirable performance with excellent energy savings. These applications are able to tradeoff speed for reduced power consumption and reduced minimum operating voltage.

Improving powerdelay performance of ultralowpower subthreshold scl circuits. Variation in delay is observed where the time period is 10. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Also circuits designed for highspeed can be used to design for ultralow power. Comparison of bulk cmos with dgmosfets has been conducted in ultralow power subthreshold digital logic design and rectifier design, emphasizing the scope of the nanoscale dgmosfet technology for future ultralow power systems. The data in the circuit should be preserved during the sleep mode to. It is shown that the power consumption of stscl circuits. Design the ultralow power digital subthreshold logic circuits in domino logic. Ultralow power digital subthreshold logic circuits. However, it reduces the gate control over the channel. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultralow power with. The aim of this study is to achieve ultralow power communication circuits operating at high frequency. Robust and energyefficient ultralowvoltage circuit. Implementation of ultralow power digital circuits using.

Ultralow power design, subthreshold circuits, dual voltage design, mixed linear integer program, gate slack. Ultra low power subthreshold mos current mode logic. Ultra low power cmos design by kyungseok kim a dissertation submitted to the graduate faculty of auburn university in partial ful. In this paper, we propose two different subthreshold logic families. It is intention in this work to explore the possibilities ofbridging the power.

Robust subthreshold logic for ultralow power operation. We analyze both cmos and pseudonmos logic families operating in subthreshold region. Description of the circuit simulation benchmark 171. Leakage current reduction using subthreshold source. Exploring cmos logic families in subthreshold region for. A novel approach is presented for implementing ultralowpower digital components and systems using sourcecoupled logic scl circuit topology, operating in. Ultralow power digital subthreshold logic circuits 1999. Minimum size pmos transistors with shorted drainsubstrate contacts are used as gatecontrolled, very high resistivity load devices. This article presents a novel and robust approach for implementing ultralow power mos current mode logic mcml circuits.